The present invention relates generally to a method of time aligning symbol data in a digitally modulated transmission system and more specifically to estimating symbol timing phase and rate offsets of a sampled digitally modulated signal having repetitive symbol sync sequences, such as 8-VSB digital television signals.
The Federal Communications Commission has adopted the Digital Television Standard developed by the Advanced Television Systems Committee (ATSC). The Digital Television Standard is designed to transmit high quality video, audio and ancillary data over a 6 MHz channel. The Standard describes the channel coding and modulation RF/transmission subsystems for terrestrial and cable applications. The modulation subsystem uses a digital data stream to modulate the transmitted signal and may be implemented in two modes: a terrestrial broadcast mode (8-VSB) delivering about 19 Mbps, and a higher data rate mode (16-VSB) delivering about 38 Mbps for cable televisionvystems where higher signal to noise is ensured.
The modulation technique implemented in the Digital Television Standard was developed by Zenith Corp. and employs vestigial sideband modulation. The overall system response of the transmitter and receiver filtering corresponds to a raised cosine filter to avoid system generated intersymbol interference. The system response is implemented with serially coupled, nominally identical root raised cosine filters in the transmitter and in the receiver.
The incoming digital data stream is randomized, forward-error-correction (FEC) encoded and interleaved. The randomized, FEC coded and interleaved data is trellis encoded as an 8-level (3-bit) one dimensional constellation. The outputs of the trellis coder are mapped into symbols that are one of eight symmetric odd-valued integer levels from xe2x88x927 to +7 units. To aid synchronization in low signal to noise and/or high multipath situations, segment and field syncs are inserted in the 10.76 Msymbols/sec symbol stream. A small pilot tone is added as well at the carrier frequency generated by offsetting the real or I channel of the complex signal containing the data and the sync pulses by 1.25 units. The offset causes the pilot tone to be in-phase with the I channel signal component. At the transmitter, the composite signal passes through a root raised cosine filter and modulates an intermediate frequency carrier signal which is up-converted to an RF frequency for transmission at the desired channel frequency. Alternately, the composite signal may be used to directly modulate the RF carrier.
Referring to FIG. 1, there is shown a representative block diagram of a VSB receiver for extracting the digital television signal data from the digitally modulated RF signal as described in the xe2x80x9cGuide to the Use of the ATSC Digital Television Standardxe2x80x9d published by the ATSC. The receiver 10 receives the UHF or VHF signal through a band-pass filter and broadband tracking filter 12. A wideband amplifier 14 increases the signal level and couples it to a first mixer 16. The mixer is driven by a 1st local oscillator 18 that tunes over a range from 978 to 1723 MHz. The 1 st local oscillator 18 is synthesized by a phase locked-loop and controlled by a microprocessor (not shown). The output of the mixer 16 is an up-converted intermediate frequency (IF) signal at 920 MHz. The IF signal is coupled to an LC filter 20 in tandem with a band-pass ceramic resonator filter 22 centered at 921 MHz. An IF amplifier 24 is placed between the two filters. The IF signal is coupled to a second mixer 26 that is driven by 2nd local oscillator 28. The 2nd local oscillator 28 is an 876 MHZ voltage controlled SAW oscillator controlled by a frequency and phase-locked loop (FPLL) synchronous detector 30. The output of the second mixer 26 is centered at 45 MHz. This IF signal drives a constant gain 44 MHZ amplifier 32. The output of the amplifier 32 is coupled to an IF SAW filter 34. The IF SAW filter 34 implements an approximation of the transmission system""s root raised cosine filter at the receiver. The output of the SAW filter 34 is coupled to the FPLL synchronous detection circuitry 30 via an AGC controlled amplifier 36.
Carrier recovery is performed on the pilot signal by the FPLL circuit 30. The operation of this circuit is described in U.S. Pat. No. 4,091,410, assigned to Zenith Corp. The configuration provides a Phase Locked Loop (PLL) function with a very wide pull-in range which insures rapid carrier acquisition. The I channel baseband data signal from the synchronous detector 30 is coupled through a low pass filter 54 to an analog-to-digital converter (A/D) 56 that is clocked by a properly phased 10.76 MHz symbol clock 58. The digital data from the A/D converter 56 is coupled to a data segment sync detector 60 having a narrow bandwidth filter for detecting from the synchronously detected random data the repetitive data segment syncs as described in U.S. Pat. No. 5,416,524, assigned to Zenith Corp. The symbol clock generator 58 free runs at a rate reasonably close to the transmitted symbol clock prior to phase locking. The data segment sync detector 60, containing a 4-symbol sync correlator 62, looks for the sync symbols occurring at the specified sync repetition rate. The output of the correlator is integrated using a segment delay line 64, with only the syncs rising to a high level, since all the other data is guaranteed to be random in nature. The clock frequency need not be locked to find the segment sync in order to recognize the segment sync. Clock phasing begins when a sync detector/confidence counter 66 reaches a predefined level indicating that the segment sync has been found. The sync detector signal from the sync detector/confidence counter 66 samples a quadrature filter 68 output during the sync time in a sampler/phase detector 70, producing an error voltage proportional to the phase difference between the receiver""s clock sampling time and the zero crossing of the quadrature filter 68 output, which corresponds to a maximum eye opening. The 4-tap quadrature filter 68 converts the segment syncs into xe2x80x9cdiscriminator S-curvexe2x80x9d signals. The sampler 70 output is coupled through an APC low pass filter 72 for adjusting the symbol clock generator 58 either higher or lower in frequency, until the proper sampling time is reached, with the symbol clock locked to the incoming data clock frequency.
A Hewlett-Packard HP 89440A Vector Signal Analyzer has been used for making measurements on 8-VSB signals. The HP 89440A includes a superheterodyne receiver having a first LO and mixer for up-converting the incoming signal to a first IF frequency. Second and third LOs and mixers respectively generate second and third IF frequencies of 40 MHz and 10 MHz. The 10 MHz IF is digitized by an analog-to-digital converter with the digitized data being down converted to baseband real and imaginary data. The real and imaginary data values are passed to a digital signal processor for FFT conversion and additional signal processing. A limitation of a superheterodyne type receiver is the need for bandwidth limiting filters between the IF stages to prevent the undesired mixer signal outputs from entering subsequent IF stages. Such filtering can mask artifacts in the transmitter signal resulting in inaccurate measurements of the operating condition.
In certain applications, such as measurements of the signal quality, a software based demodulator could be used to demodulate the received IF signal. A software based demodulator can bring greater flexibility in processing the digitally modulated signal. For example, in some measurements, it is desirable to limit the amount of signal filtering to prevent the masking of desirable characteristics in the signal. This would include narrow band-limiting filters in the IF signal. channel and the transmission system""s receiver filter. In other cases the demodulator has to provide signal samples representative of the digitally modulated transmitter signal that have been filtered with the transmission system""s receiver filter. This type of flexibility may be achieved by employing a signal processing section having an unfiltered hardware acquisition front end and a software based demodulator. The software demodulator can generate signal samples that have and have not been filtered by the transmission system""s receiver filter so signal quality comparisons can be made between the different signal samples. Additionally, it can provide flexible demodulation design for adapting to the needs of different types of measurements. The incoming signal should be sampled at a rate sufficient to prevent aliasing in the software demodulator and to provide the signal samples necessary to make certain types of measurements, such as an eye diagram display. As with all demodulators, accurate timing alignment is important to recover the transmitted digital symbols, but it is especially important for accurately measuring signal quality. For software based demodulators, there is an additional need to provide a computationally efficient timing alignment method, which is not addressed in prior art hardware based demodulators.
Accordingly, an object of the present invention is deriving symbol timing phase and rate offsets in a sampled digitally modulated signal having repetitive symbol sync sequences wherein the signal samples have not been filtered by the system""s receiver filter.
Another object of the present invention is improving system processing throughput by reducing filter processing of the signal samples of the digitally modulated signal for deriving symbol timing phase and rate offsets.
A further object of the present invention is establishing an efficient and accurate method of estimating the rate offset of the symbol sync sequences in a digitally modulated signal having repetitive symbol sync sequences.
The present invention is a method of estimating symbol timing phase and rate offsets in signal samples having repetitive symbol sync sequences representative of the digitally modulated radio frequency signal generated by a transmission system having a transmitter and a receiver with an overall system response implemented with serially coupled transmitter and receiver filters for avoiding system generated intersymbol interference and machine readable medium having stored thereon a series of instructions, which when executed by a processor of a transmission receiver, estimates the symbol timing phase and rate offset in the signal samples. The method and instructions include the steps of processing the signal samples for producing filtered signal samples within selected subranges of a block of the signal samples containing the symbol sync sequences and generating symbol timing phase and rate offset values using the filtered signal samples in the selected subranges. The filtered signal samples are resampled in the selected subranges using an interpolating filter having filter coefficients derived from the symbol timing phase and rate offset values and the generating and resampling steps are repeated with the generating step calculating updated symbol timing phase and rate offset values from the resampled filtered signal samples for deriving updated filter coefficients for the resampling process until a limit value is reached. The generating step further includes the additional steps of determining incremental changes in the timing phase offset values and a count on the number of times the generating step is performed and returning the current calculated timing phase and rate offset values when the incremental changes are reduced to or below selected values or when the genrateing stop count exceeds a selected value.
System processing throughput improves by correlating the block of signal samples with a reference pattern of ideal symbol sync sequences for determining a location of a peak cross-correlation value for estimating locations of the symbol sync sequences in the block of signal samples and filtering the signal samples in the selected subranges about the estimated symbol sync sequence locations using a transmission system receiver filter. The filtered signal samples for the subranges are stored in a buffer memory.
The generation of the timing phase offset value includes the steps of correlating the signal samples of the subranges with the reference pattern of ideal symbol sync sequences for determining a correlation peak location and correlating the signal samples of the subranges with a reference pattern of quadrature symbol sync sequences for determining the symbol timing phase offset value. The generation of the timing rate offset values includes the step of correlating each subrange of signal samples with the reference pattern of the quadrature symbol sync sequences for determining the symbol timing rate offset value.
The correlating step for the timing phase offset value includes the steps of calculating parameters of a line segment having a zero crossing using data values from the correlation of the signal samples of the subranges and the reference pattern of quadrature symbol sync sequences that includes the quadrature correlation data value corresponding to the correlation peak location determined with the reference pattern of ideal symbol sync sequences and estimating a horizontal distance from the smallest quadrature correlation data value to the line segment zero crossing point for use as the symbol timing phase offset update value.
The correlating step for the timing rate offset value includes the step of modeling a rate offset from individual timing rate offsets for each subrange using a linear model. The modeling step includes the steps of determining weighting values of a least-squares fit linear model based on the number of segments in the block of signal samples and estimating the symbol timing rate offset update value with a summation process using the weighting values and zero lag data values from each of the correlations of the subrange of signal samples with the quadrature sync symbol pattern.
The generating of the timing phase and rate offset values includes the calculating step of combining the current symbol timing phase and rate offset values with previous symbol timing phase and rate offset values. The resampling step further includes the step of filtering the signal samples of the subranges using a fractional-delay FIR filter implemented by a Lagrange interpolating polynomial.
The objects, advantages and novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawings.